1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device provided with a measurement circuit of internal power-supply voltage.
2. Description of Related Art
In recent years, the power-supply voltage circuit of a semiconductor device has become complex and a plurality of internal power-supply voltages, such as a step-down voltage, a step-up voltage, a negative voltage, and a half VCC, which is ½ of a power-supply voltage, are used in one chip. Furthermore, because the breakdown voltage of a device has become lower due to miniaturization, the trend toward lower voltages has become more prevalent. When different voltages are generated within a device, this destroys the device or worsens the characteristics of the device. Therefore, an improvement in the accuracy of an internal power-supply voltage is required.
In order to obtain high-accuracy potentials, it is necessary to measure internal potentials. Parallel measurements have been increasingly adopted in order to reduce measurement cost in measurements on a wafer. However, because the number of test pins in a test device is insufficient, there has been increasing need for a measurement circuit of internal power-supply voltage which can be shared with external pins and permits high-accuracy measurements at low voltages.
In taking out an internal potential of a mold-resin sealed chip from the chip and measuring the potential, it is necessary that an external terminal and a terminal for outputting the internal potential be shared. In the case where terminals are shared like this, it has become an important problem to take measures to ensure that even when overshoots of not less than a power-supply voltage or undershoots of not more than GND enter external pins, this does not affect the internal potential.
FIG. 6 shows a circuit configuration of a switch circuit described in Japanese Patent No. 3583482. As shown in FIG. 6, the switch circuit has such a configuration that an n-channel MOS transistor T1 and a p-channel MOS transistor T2 are connected in series. An external terminal 114 is connected to a drain of the MOS transistor T1. Sources of the n-channel MOS transistor T1 and the p-channel MOS transistor T2 are connected together, and a drain of the p-channel MOS transistor T2 and an internal power-supply circuit are connected together.
A test mode specifying signal, for example, S1 in FIG. 6 is inputted to a gate of the n-channel MOS transistor T1. A test mode specifying signal S1 inverted by an inverter 116 is inputted to a gate of the p-channel MOS transistor T2. Therefore, the switch circuit shown in FIG. 6 comes to an on state when the test mode specifying signal S1 is HIGH and comes to an off state when the test mode specifying signal S1 is LOW.
With the aid of FIG. 7, a description will be given here of the cut-off characteristics for a voltage inputted to the switch from the external terminal 114. FIG. 7 is a diagram showing the cross section of portions corresponding to the n-channel MOS transistor T1 and p-channel MOS transistor T2 of the switch circuit of FIG. 6. In the example shown in FIG. 7, a case where a p-type S1 substrate is used is shown diagrammatically.
As shown in FIG. 7, the n-channel MOS transistor is formed in a p-well and the p-channel MOS transistor is formed in an n-well. Usually, a p-well is biased to a GND potential VSS or a substrate bias VBB. An n-well is biased to ext. VCC, an external power-supply voltage.
Therefore, when the test mode specifying signal SI comes to a HIGH state (=ext. VCC), an n-type inversion layer is formed just under the gate of the n-channel MOS transistor and conduction occurs. And a LOW state (=0 V) is applied to the gate of the p-channel MOS transistor, a p-type inversion layer is formed just under the gate, and conduction occurs.
When the potential of the external terminal 114 exceeds a VCC and overshoots to a positive value, because the gate potential of the n-channel MOS transistor gate is a VCC, the n-type inversion layer disappears in the vicinity of the drain of the n-channel MOS transistor and the conducting state becomes cut off. On the other hand, when the potential of the external terminal 114 becomes lower than 0 V and undershoots to a negative value, because the gate potential of the p-channel MOS transistor is 0 V, the p-type inversion layer disappears in the vicinity of the source of the p-channel MOS transistor and the conducting state becomes cut off.
As described above, in the switch circuit of FIG. 6, because the n-channel MOS transistor and the p-type MOS transistor are connected in series, the conducting state becomes cut off both when the potential of the external terminal 114 overshoots to a positive value and when the potential of the external terminal 114 undershoots to a negative value. As a result, an overshooting voltage or an undershooting voltage is not applied directly to the internal circuit connected to the internal power-supply circuit and it is possible to prevent internal stored information and the like from being destroyed.